IGNOU BPHET-143 Solved Question Paper PDF Download

IGNOU BPHET-143 Previous Year Solved Question Paper in Hindi

IGNOU BPHET-143 Previous Year Solved Question Paper in English

Q1. (a) List any four factors that affect the conductivity of semiconductors. (b) Calculate the maximum input voltage that can be applied to a non-inverting amplifier using op-amp with gain 10 to get distortion free output if supply voltage Vcc is + 5 V. (c) Convert the hex number BA6₁₆ into binary number. (d) If change in load voltage is 10 mV and nominal load voltage is 10 V, calculate the percentage (%) source regulation of a voltage regulator. (e) What are the advantages of negative feedback in amplifiers? (f) If the peak voltage across a transformer secondary is 100 V, what is the d.c. voltage value Vdc of (i) a half wave rectifier, and (ii) a full wave rectifier? (g) What is CMRR for an op-amp? (h) What is the frequency of the displayed signal if one complete cycle covers 5 horizontal divisions on the CRT screen, with a time/div setting of 2μs/div?

Ans. (a) Four factors that affect the conductivity of semiconductors are:

• Temperature: As temperature increases, more covalent bonds break, generating more electron-hole pairs. This increases the number of charge carriers and hence, increases conductivity.
• Doping: The process of intentionally adding impurities (like trivalent or pentavalent atoms) to a pure semiconductor is called doping. Increasing the doping concentration increases the number of free electrons or holes, thereby significantly increasing conductivity.
• Illumination: When light (photons) of sufficient energy falls on a semiconductor, it can create electron-hole pairs. This increase in charge carrier concentration leads to an increase in conductivity (photoconductivity).
• Electric Field: Applying a strong external electric field can sometimes lead to the breakdown of covalent bonds or increase the drift velocity of charge carriers, thus affecting the conductivity.

(b)

For a non-inverting amplifier, the maximum output voltage (Vₒᵤₜ) without distortion is approximately equal to the saturation voltage (Vₛₐₜ), which is slightly less than the supply voltage (Vcc). For a distortion-free output, we can assume Vₒᵤₜ(max) ≈ Vcc = +5 V.

Given: Gain, A = 10; Vcc = +5 V

The output voltage is given by: Vₒᵤₜ = A × Vᵢₙ

Therefore, the maximum input voltage (Vᵢₙ(max)) will be:

Vᵢₙ(max) = Vₒᵤₜ(max) / A

Vᵢₙ(max) = 5 V / 10 = 0.5 V

Thus, a maximum input voltage of

0.5 V

can be applied for a distortion-free output.

(c)

To convert the hexadecimal number BA6₁₆ to binary, we convert each hex digit into its 4-bit binary equivalent.

• B (which is 11) = 1011
• A (which is 10) = 1010
• 6 = 0110

Combining them, we get: 101110100110₂

Hence,

BA6₁₆ = 101110100110₂

.

(d)

The question likely means “load regulation,” as source regulation relates to changes in the input voltage. Load regulation measures the change in output voltage due to a change in load current.

Percentage (%) Load Regulation = [(Vₙₗ – Vբₗ) / Vբₗ] × 100

Here, the change in load voltage (Vₙₗ – Vբₗ) is given as 10 mV = 0.01 V.

The nominal (full) load voltage Vբₗ = 10 V.

Percentage Regulation = (0.01 V / 10 V) × 100 = 0.001 × 100 =

0.1%

(e) Advantages of negative feedback in amplifiers:

• Gain Stabilization: It makes the amplifier’s gain less dependent on variations in transistor parameters or temperature.
• Increased Bandwidth: It extends the frequency range over which the amplifier provides useful gain.
• Reduction in Distortion: It reduces non-linear distortion, resulting in a cleaner output signal.
• Reduction in Noise: It reduces the effect of noise generated within the amplifier.
• Modification of Input and Output Impedances: It can increase or decrease the input impedance and decrease or increase the output impedance as required by the application.

(f)

Given: Peak voltage across the secondary, Vₘ = 100 V.

(i) For a

half-wave rectifier

, the DC voltage (Vdc) is:

Vdc = Vₘ / π = 100 V / π ≈

31.83 V

(ii) For a

full-wave rectifier

(center-tapped or bridge), the DC voltage (Vdc) is:

Vdc = 2Vₘ / π = 2 × 100 V / π ≈

63.66 V

(g) CMRR (Common Mode Rejection Ratio):

CMRR is the ratio of an op-amp’s differential gain (A𝘥) to its common-mode gain (A𝘤ₘ). It is often expressed in decibels (dB).

CMRR = 20 log₁₀(|A𝘥 / A𝘤ₘ|)

It is a measure of an op-amp’s ability to reject signals that are common to both of its input terminals. An ideal op-amp has an infinite CMRR. A higher CMRR value indicates better performance.

(h)

The time period (T) of the signal is calculated as:

T = (Number of horizontal divisions) × (time/div setting)

T = 5 div × 2 μs/div = 10 μs = 10 × 10⁻⁶ s

The frequency (f) of the signal is the reciprocal of the time period:

f = 1 / T

f = 1 / (10 × 10⁻⁶ s) = 100,000 Hz =

100 kHz

Q2. (a) With a suitable diagram, explain the formation of depletion region in a p-n junction. What happens to the depletion region when the reverse bias voltage is increased? (b) What is photovoltaic effect? Using a suitable diagram, explain the working of a solar cell. (c) An n-p-n transistor with β = 50 is used in a CE circuit shown in Fig. 1 with Vcc = 10 V and Rc = 2 kΩ. The self bias is obtained by connecting a 100 kΩ resistance (Rb) from collector to base. Assume Vbe = 0.7 V. Determine the Q-point for the circuit.

Ans. (a) Formation of Depletion Region in a p-n Junction: When a p-type semiconductor is brought into contact with an n-type semiconductor, a p-n junction is formed.

1. Diffusion of Charge Carriers: Due to the concentration gradient, holes (majority carriers) from the p-side diffuse into the n-side, and electrons (majority carriers) from the n-side diffuse into the p-side.
2. Recombination and Formation of Immobile Ions: When an electron and a hole meet, they neutralize each other (recombination). When an electron leaves the n-region, it leaves behind a positive immobile donor ion. Similarly, when a hole leaves the p-region, it leaves behind a negative immobile acceptor ion.
3. Creation of Depletion Region: The accumulation of these immobile ions on either side of the junction creates a region that is depleted of mobile charge carriers (electrons and holes). This region is called the depletion region or space charge region . There is a layer of positive ions on the n-side and a layer of negative ions on the p-side.
4. Potential Barrier: The charge of these immobile ions creates an internal electric field (E) directed from the n-side to the p-side. This field opposes further diffusion of charge carriers. The potential difference created by this electric field is called the potential barrier .

Effect of Increasing Reverse Bias Voltage:

When a reverse bias is applied to the p-n junction (connecting the p-side to the negative terminal and the n-side to the positive terminal of a battery), the external voltage aids the internal electric field. This pulls the holes in the p-region and electrons in the n-region away from the junction. As a result,

the width of the depletion region increases

, and the potential barrier also increases.

(b) Photovoltaic Effect and Working of a Solar Cell:

Photovoltaic Effect:

It is the process in which a material (typically a semiconductor) generates an electric voltage or current when exposed to light. When photons of sufficient energy strike the semiconductor, they transfer their energy to electrons, creating electron-hole pairs. An internal electric field within the material separates these charge carriers, resulting in a potential difference.

Working of a Solar Cell:

A solar cell is essentially a large p-n junction diode designed to convert light energy into electrical energy using the photovoltaic effect.

1. Light Absorption: When sunlight strikes the surface of the solar cell, photons penetrate the semiconductor material.
2. Generation of Electron-Hole Pairs: If a photon’s energy is greater than the semiconductor’s band gap, it creates an electron-hole pair by breaking a covalent bond.
3. Separation of Charge Carriers: The internal electric field present in the depletion region of the p-n junction separates these generated electron-hole pairs. The field pushes electrons towards the n-side and holes towards the p-side.
4. Development of Voltage: Due to this separation, electrons accumulate in the n-region and holes in the p-region, developing a voltage (photovoltage) across the p-n junction.
5. Current Flow: If an external load (like a bulb) is connected to the terminals of the solar cell, the accumulated electrons flow through the external circuit to the p-side, creating an electric current (photocurrent) and powering the load.

(c) Determination of the Q-point:

Given: Vcc = 10 V, Rc = 2 kΩ, Rb = 100 kΩ, β = 50, Vbe = 0.7 V.

This is a collector-feedback bias circuit.

Applying Kirchhoff’s Voltage Law (KVL) to the base-emitter loop (from Vcc through Rc and Rb to the emitter):

Vcc = (Ib + Ic)Rc + IbRb + Vbe

Since Ic = βIb, we can write:

Vcc = (Ib + βIb)Rc + IbRb + Vbe

Vcc = Ib(1 + β)Rc + IbRb + Vbe

Vcc – Vbe = Ib [Rb + (1 + β)Rc]

Substitute the values to find Ib:

10 – 0.7 = Ib [100 kΩ + (1 + 50) × 2 kΩ]

9.3 = Ib [100 kΩ + 51 × 2 kΩ]

9.3 = Ib [100 kΩ + 102 kΩ]

9.3 = Ib [202 kΩ]

Ib = 9.3 V / 202 kΩ = 0.04604 mA = 46.04 μA

Now, we can calculate the collector current (Ic):

Ic = β × Ib = 50 × 46.04 μA = 2302 μA =

2.302 mA

Now, calculate the collector-emitter voltage (Vce). Applying KVL to the collector-emitter loop:

Vcc = (Ib + Ic)Rc + Vce

Vce = Vcc – (Ib + Ic)Rc

Vce = 10 V – (0.04604 mA + 2.302 mA) × 2 kΩ

Vce = 10 V – (2.348 mA) × 2 kΩ

Vce = 10 V – 4.696 V =

5.304 V

Thus, the operating point (Q-point) of the circuit is:

Q = (Vce, Ic) = (5.304 V, 2.302 mA)

.

Q3. (a) Prove the following Boolean equation using the laws of Boolean algebra: A’BC’ + A’BC + AB’C + ABC = AB + BC + AC. (b) For the following logic equation: Y = A’B’C + A’BC’ + AB’C’ + ABC (i) Write its truth table. (ii) Simplify using K-map and draw its circuit after simplification. (c) Write the truth table of a Full Adder. Simplify the expressions for SUM and CARRY.

Ans. (a) Proof of the Boolean Equation: The given equation `A’BC’ + A’BC + AB’C + ABC = AB + BC + AC` is incorrect as written. The simplification of the left side, `A’BC’ + A’BC + AB’C + ABC`, is `A’B + AC`. There is likely a typographical error in the question. A common, correct identity is `A’BC + AB’C + ABC’ + ABC = AB + BC + AC`. We will prove this corrected equation. To Prove: `LHS = A’BC + AB’C + ABC’ + ABC = AB + BC + AC = RHS` We can add the term `ABC` two more times to the LHS, as `X + X = X`. This facilitates grouping. LHS = A’BC + AB’C + ABC’ + ABC + ABC + ABC Rearranging the terms for grouping: LHS = (A’BC + ABC) + (AB’C + ABC) + (ABC’ + ABC) Now, factor out the common terms from each group (using the law `X Y + X’Y = Y`):

• (A’BC + ABC) = BC(A’ + A) = BC(1) = BC
• (AB’C + ABC) = AC(B’ + B) = AC(1) = AC
• (ABC’ + ABC) = AB(C’ + C) = AB(1) = AB

Combining these simplified terms:

LHS = BC + AC + AB

This is equal to the RHS (AB + BC + AC).

Hence proved (assuming the typo in the question where `A’BC’` should have been `ABC’`).

(b) Simplification of Boolean Equation:

The given equation is: `Y = A’B’C + A’BC’ + AB’C’ + ABC`

(i) Truth Table:

A	B	C	Y
0	0	0	0
0	0	1	1 (A’B’C)
0	1	0	1 (A’BC’)
0	1	1	0
1	0	0	1 (AB’C’)
1	0	1	0
1	1	0	0
1	1	1	1 (ABC)

(ii) Simplification using K-map:

We use a 3-variable K-map:

 BC 00 01 11 10 +---+---+---+---+A 0| 0 | 1 | 0 | 1 | +---+---+---+---+ 1| 1 | 0 | 1 | 0 | +---+---+---+---+

There are no adjacent 1s to form groups of 2, 4, or 8. This is a “checkerboard” pattern, which indicates that the expression cannot be simplified further using Boolean algebra. It represents an XOR/XNOR type function but not a simple one. Therefore, the simplified expression is the original expression itself: Y = A’B’C + A’BC’ + AB’C’ + ABC Circuit after simplification: Since the expression is not simplified, the circuit is drawn directly from the SOP (Sum of Products) form. It requires four 3-input AND gates, one 4-input OR gate, and three NOT gates (to create the complements of A, B, and C). (c) Full Adder: A full adder is a combinational logic circuit that adds three bits (two input bits A and B, and a carry-in bit Cin). It produces two outputs: a Sum (S) and a Carry-out (Cout). Truth Table:

A	B	Cin	S (Sum)	Cout (Carry)
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Simplification of Expressions: For the Sum (S): From the truth table, S = 1 whenever there is an odd number of 1s in the inputs. S = A’B’Cin + A’BCin’ + AB’Cin’ + ABCin This is the expression for a 3-input XOR function. S = A ⊕ B ⊕ Cin For the Carry-out (Cout): From the truth table, Cout = 1 whenever two or more inputs are 1. Cout = A’BCin + AB’Cin + ABCin’ + ABCin This can be simplified using a K-map:

 AB 00 01 11 10 +---+---+---+---+Cin 0| 0 | 0 | 1 | 0 | +---+---+---+---+ 1| 0 | 1 | 1 | 1 | +---+---+---+---+

By grouping the 1s, we get three pairs:

• Pair 1: (m3, m7) -> BCin
• Pair 2: (m5, m7) -> ACin
• Pair 3: (m6, m7) -> AB

Thus, the simplified expression is: Cout = AB + BCin + ACin

Q4. (a) Plot the frequency response curve for an RC-coupled amplifier with a voltage gain of 1000 in the frequency range 400 Hz to 25 kHz and a 3 dB drop on either side of these frequencies at 80 Hz and 40 kHz. Calculate the gain in dB at the cut-off frequencies also (80 Hz and 40 kHz). (b) Draw a labelled circuit diagram and explain the working of Colpitts’ oscillator. Write the expression for its frequency of oscillation. (c) Draw the labelled circuit diagram and derive the expression for voltage gain of inverting amplifier using Op-Amp.

Ans. (a) Frequency Response of an RC-Coupled Amplifier: Given: Mid-band voltage gain, Aᵥ(mid) = 1000 Mid-band frequency range = 400 Hz to 25 kHz Lower cut-off frequency, fₗ = 80 Hz Upper cut-off frequency, fₕ = 40 kHz 1. Calculation of Gain in dB at Mid-band: Aᵥ(dB) = 20 log₁₀(Aᵥ) Aᵥ(dB) = 20 log₁₀(1000) = 20 × 3 = 60 dB 2. Calculation of Gain in dB at Cut-off Frequencies: The cut-off frequencies are also called the -3dB frequencies. At these frequencies, the gain drops by 3 dB from the mid-band gain. Gain (dB) at cut-off = Mid-band Gain (dB) – 3 dB Gain (dB) at cut-off = 60 dB – 3 dB = 57 dB Therefore, the gain at both 80 Hz and 40 kHz is 57 dB. 3. Frequency Response Curve: The curve is plotted with Frequency (on a logarithmic scale) on the x-axis and Voltage Gain (in dB) on the y-axis.

• The curve will be approximately flat at 60 dB between 400 Hz and 25 kHz. This is the mid-band .
• As frequency decreases below 400 Hz, the gain drops, reaching 57 dB at 80 Hz (fₗ) .
• As frequency increases above 25 kHz, the gain drops, reaching 57 dB at 40 kHz (fₕ) .
• The Bandwidth (BW) is fₕ – fₗ = 40 kHz – 80 Hz ≈ 39.92 kHz.

(b) Colpitts’ Oscillator:

The Colpitts oscillator is a type of LC (inductor-capacitor) electronic oscillator that generates sinusoidal waves.

Circuit Diagram:

It consists of an amplifier (typically a transistor in CE configuration) and a feedback network. The feedback network is an LC resonant circuit (tank circuit) made of one inductor (L) and two capacitors (C₁ and C₂) forming a capacitive voltage divider.

Working Principle:

1. Start-up: When power is applied, random noise in the collector current is amplified.
2. Resonance: This amplified noise contains various frequency components. The tank circuit (L, C₁, C₂) allows oscillations only at its resonant frequency. The capacitors C₁ and C₂ charge and discharge, causing an oscillating current to flow through L.
3. Feedback: The capacitive voltage divider formed by C₁ and C₂ feeds a fraction of the output voltage (from the collector) back to the input (base). The junction between C₁ and C₂ is grounded, providing a 180° phase shift by the tank circuit.
4. Sustained Oscillations: The CE amplifier itself provides a 180° phase shift. Thus, the total phase shift around the loop becomes 360° (or 0°). If the magnitude of the loop gain is greater than or equal to one (Barkhausen’s criterion), sustained oscillations are produced.

Frequency of Oscillation:

The frequency of oscillation is determined by the components of the tank circuit:

f = 1 / (2π√(L × Cₑq))

Where Cₑq is the series combination of C₁ and C₂: Cₑq = (C₁ × C₂) / (C₁ + C₂)

(c) Inverting Op-Amp Amplifier:

This is an op-amp based amplifier that amplifies and phase-shifts the input signal by 180°.

Circuit Diagram:

Derivation of Voltage Gain:

We use two properties of an ideal op-amp:

1. The input impedance is infinite (i.e., no current flows into the op-amp’s input terminals).

2.

Virtual Ground Concept:

Since the non-inverting input (+) is grounded (0V), and the op-amp’s open-loop gain is very high, negative feedback forces the voltage at the inverting input (-) to also be at 0V. Hence, V⁻ ≈ V⁺ = 0 V.

Now, apply Kirchhoff’s Current Law (KCL) at node V⁻.

The current flowing through resistor Rᵢₙ (Iᵢₙ):

Iᵢₙ = (Vᵢₙ – V⁻) / Rᵢₙ

Since V⁻ = 0 V,

Iᵢₙ = Vᵢₙ / Rᵢₙ —(1)

The current flowing through the feedback resistor Rբ (Iբ):

Iբ = (V⁻ – Vₒᵤₜ) / Rբ

Iբ = (0 – Vₒᵤₜ) / Rբ = -Vₒᵤₜ / Rբ —(2)

Since no current enters the op-amp, the current Iᵢₙ must flow through Rբ.

Therefore, Iᵢₙ = Iբ

From equations (1) and (2):

Vᵢₙ / Rᵢₙ = -Vₒᵤₜ / Rբ

Rearranging for the voltage gain (Aᵥ):

Vₒᵤₜ / Vᵢₙ = -Rբ / Rᵢₙ

Thus, the voltage gain of the inverting amplifier is:

Aᵥ = -Rբ / Rᵢₙ

The negative sign indicates the 180° phase shift.

Q5. (a) Explain with a labelled diagram how a Zener diode can be used for shunt voltage regulation. (b) Explain briefly the functions of the following components of CRO: (i) Electron Gun assembly (ii) Deflection system (iii) Time base circuit (c) Draw the circuit diagram of an astable multivibrator using IC 555 timer. Explain its working with the help of associated waveforms.

Ans. (a) Zener Diode as a Shunt Voltage Regulator: A Zener diode can be used to build a simple and effective shunt (parallel) voltage regulator, which provides a stable DC voltage across a load despite variations in input voltage or load current. Labelled Diagram: Working Principle:

1. Circuit Configuration: The Zener diode is connected in parallel with the load resistor (Rₗ) and is operated in its reverse-biased condition. A series resistor (Rₛ) is used to limit the current from the unregulated input voltage (Vᵢₙ).
2. Zener Breakdown: The Zener diode is chosen such that its Zener breakdown voltage (V₂) is equal to the desired regulated output voltage (Vₗ). When Vᵢₙ is greater than V₂, the diode enters the Zener breakdown region and maintains an almost constant voltage (V₂) across its terminals.
3. Voltage Regulation:
   • If the input voltage (Vᵢₙ) increases: The voltage drop across Rₛ (Vᵢₙ – V₂) increases. This increases the total current (Iₛ) flowing through Rₛ. Since the load voltage is constant at V₂, the load current (Iₗ) remains constant. The excess current (Iₛ – Iₗ) flows through the Zener diode (I₂). Thus, the Zener diode shunts the extra current, keeping the output voltage stable.
   • If the load resistance (Rₗ) decreases (i.e., load current Iₗ increases): The current flowing through the Zener diode (I₂) decreases, keeping the total current Iₛ (which is I₂ + Iₗ) nearly constant. This maintains a constant voltage drop across Rₛ, and therefore the output voltage remains regulated at V₂.

In this way, the Zener diode acts as a variable current sink to keep the output voltage constant.

(b) Functions of CRO Components:

The Cathode Ray Oscilloscope (CRO) is a versatile instrument used to observe and measure the waveform of electrical signals. Its main components are:

(i) Electron Gun Assembly:

Its main function is to produce a narrow, focused, and high-velocity beam of electrons. It consists of:

• Cathode: A heated filament that emits electrons by thermionic emission.
• Control Grid: It is at a negative potential with respect to the cathode and controls the intensity of the electron beam, thus controlling the brightness of the spot on the screen.
• Focusing and Accelerating Anodes: These are at positive potentials and serve to accelerate the electrons towards the screen and focus them into a fine spot.

(ii) Deflection System:

This system deflects the electron beam horizontally and vertically. It consists of two pairs of plates:

• Vertical Deflection Plates (Y-plates): The input signal is applied here. The voltage between these plates deflects the electron beam vertically, in proportion to the instantaneous amplitude of the signal.
• Horizontal Deflection Plates (X-plates): A ramp voltage generated by the time base circuit is applied here, which sweeps the beam horizontally across the screen at a constant speed.

(iii) Time Base Circuit:

Also called the sweep generator. Its primary function is to generate a

sawtooth

voltage wave.

• This wave is applied to the horizontal deflection plates.
• During the ramp portion of the voltage, the electron spot moves from left to right across the screen at a constant speed, creating a linear scale for time.
• At the end of the ramp, the voltage rapidly drops back to zero, causing the spot to return quickly to the left side of the screen (flyback).
• The ‘Time/Div’ control adjusts the speed of this ramp, allowing the user to view signals of different frequencies on the screen.

(c) Astable Multivibrator using IC 555 Timer:

An astable multivibrator is a circuit that has no stable state; it continuously switches between two states (HIGH and LOW), generating a rectangular wave.

Circuit Diagram:

Working and Associated Waveforms:

1. Start-up: When power is first applied, assume the capacitor C is initially uncharged. The voltage across it (connected to pins 2 and 6) is less than 1/3 Vcc. This activates the trigger comparator, which sets the internal flip-flop. Consequently, the output (pin 3) goes HIGH , and the discharge transistor (at pin 7) is turned OFF.
2. Capacitor Charging: With the discharge transistor off, the capacitor C begins to charge towards Vcc through resistors Rₐ and Rᵦ.
3. Reaching Threshold: When the capacitor voltage charges up to 2/3 Vcc (the threshold level at pin 6), the threshold comparator activates and resets the flip-flop.
4. Capacitor Discharging: As the flip-flop is reset, the output (pin 3) goes LOW , and the discharge transistor (pin 7) is turned ON, connecting pin 7 to ground. Now, the capacitor C begins to discharge towards ground through resistor Rᵦ.
5. Reaching Trigger: When the capacitor voltage discharges down to 1/3 Vcc (the trigger level at pin 2), the trigger comparator sets the flip-flop again.
6. This cycle (1-5) repeats continuously, generating a continuous rectangular wave at pin 3.

Associated Waveforms:

In the waveforms, the capacitor voltage (Vc) charges and discharges between 1/3 Vcc and 2/3 Vcc, while the output voltage (Vout) switches between HIGH and LOW.